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Micrel, Inc.
The following circuit guidelines should be adhered to for
optimum circuit performance:
1. The V CC bypass capacitor must be placed close to the
VDD and ground pins. It is critical that the etch length
between the decoupling capacitor and the VDD &
GND pins be minimized to reduce pin inductance.
2. A ground plane is recommended to minimize parasitic
inductance and impedance of the return paths. The
MIC44F18 family of drivers is capable of high peak
currents and very fast transition times. Any
impedance between the driver, the decoupling
capacitors and the external MOSFET will degrade the
performance of the circuit.
3. Trace out the high di/dt and dv/dt paths, as shown in
Figures 7 and 8 and minimize etch length and loop
area for these connections. Minimizing these
parameters decreases the parasitic inductance and
the radiated EMI generated by fast rise and fall times.
MIC44F18/19/20
February 2011
15
M9999-020111
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